The present invention relates generally to the field of switching systems, and more particularly to switching fabrics that can be configured to meet different switching requirements.
Advances in switching technology and the introduction of commercial chipsets have made centralized switching engines more desirable. Conventional switching engines, however, with fixed modules or elements connected over a backplane, have bandwidth limitations that limit the effectiveness of the new switching technologies.
Conventional backplanes for Wide Area Networks and Local Area Networks use one three types of architectures: bus, ring, or star. FIG. 1 is a block diagram of a bus-based architecture with three elements 100, 110, and 120, using a shared bus 130. Bus-based architectures usually distribute the switching function, or "switching fabric," by incorporating parts of the fabric, 102, 112, and 122, into bus access logic 104, 114, and 124, respectively, of elements 100, 110, and 120, respectively.
Bus-based architectures offer some cost advantages because new elements only add costs for connectors and module space. Distributing switching functions in such architectures, however, can increase other costs. For example, a bus-based architecture may require memories to be replicated in all of the elements, or may require mechanisms to provide either distributed or centralized bus access. In addition, the bus limits the bandwidth of the system.
Merely adding a centralized fabric to a bus-based system does not necessarily create significant benefits. FIG. 2 is a block diagram of a system with a centralized switch fabric 240. The system, however, not only requires significant bus-access functions but increases bus usage. Traffic must travel from the receiving point, across the backplane to the switching fabric, and then back again over the backplane to the transmitting point. This doubles the bus traffic. Although dual buses could relieve the load from such doubling, that solution would further increase costs.
An alternative to the bus-based architecture is a ring-based architecture, which is often used in stackable units. FIG. 3 is a block diagram of such an architecture in which elements 300, 310, and 320 are connected in a ring through ring access components 305, 315, and 325. This architecture makes expansion easy when the ring can be broken, which offers special advantages for stacks of separate boxes. Rings are difficult to use in a chassis, however, because they require active elements in each slot to complete the ring, even if that slot has no element.
As with busses, the bandwidth of the ring, which requires a parallel path for higher bandwidth systems, limits the bandwidth of the system. Also, as with busses, applying centralized switching functions is difficult, and ring architectures do not provide significant cost or performance advantages by centralizing.
Centralization has been effective, however, for star-based architectures, which have emerged with the advent of significantly less expensive integrated circuit switching functions. For example, products have been built for both 10/100 Mbps Ethernet and ATM. These architectures use a central switching fabric with one or more dedicated port connections to each slot.
FIG. 4 is a block diagram of such a product in which elements 400, 410, and 420 include link access components 405, 415, and 425, respectively, and element 420 is the only element with switch fabric 428. This star-based design allows the use of low cost switching, and its bandwidth is limited only by the number of slots, the bandwidth of the switching chips, and the bandwidth of the channels to each element. Multiple paths to the slots, increase the bandwidth of this architecture as needed.
Another advantage of this architecture is a lower cost of the I/O module because the communication over the backplane link is in the proper switching format. Also, because the direct connection to the switch is operating in a "native" mode, there is no need for buffering or other sophisticated access techniques at the card level.
The disadvantage of this design, however, is that the chassis is relatively inflexible. For example, a chassis with eight I/O slots with two channels to each slot is inherently designed for sixteen times the bandwidth of the interconnect. The fixed connection between a switch point and the slot cannot be changed, for example, to only eight switched interconnects or to use only a single interconnect path to a module. This limitation requires that the chassis be purchased initially in a complete switching configuration, greatly increasing the initial cost. For example, existing designs often incur more than 50% of the cost of a port in the base chassis and switching module, and unused ports or underused ports cost the same as fully used ports.